1. Field of the Invention
The present invention generally relates to ferroelectric memory devices, and more particularly, to a ferroelectric memory device which controls boost of voltages for driving cell arrays.
2. Description of the Background Art
Generally, a ferroelectric random access memory (hereinafter, referred to as ‘FRAM’) has attracted considerable attention as next generation memory device because it has a data processing speed as fast as a DRAM and conserves data even after the power is turned off.
The FRAM includes capacitors similar to the DRAM, but the capacitors have a ferroelectric substance for utilizing the characteristic of a high residual polarization of the ferroelectric substance in which data is removed low even after eliminating an electric field applied thereto.
FIG. 1 is a characteristic curve illustrating a hysteresis loop of a general ferroelectric substance. As shown in FIG. 1, a polarization induced by an electric field does not vanish but keeps some strength (‘d’ or ‘a’ state) even after the electric field is cleared due to existence of a residual (or spontaneous) polarization. These ‘d’ and ‘a’ states may be assigned to binary values of ‘1’ and ‘0’ for use as a memory cell.
FIG. 2 is a structural diagram illustrating a unit cell of the FRAM device. As shown in FIG. 2, the unit cell of the conventional FRAM is provided with a bitline B/L arranged in one direction and a wordline W/L arranged in another direction vertical to the bitline B/L. A plateline P/L is arranged parallel to the wordline and spaced at a predetermined interval. The unit cell is also provided with a transistor T1 having a gate connected to an adjacent wordline W/L and a source connected to an adjacent bitline B/L, and a ferroelectric capacitor FC1 having the first terminal of the two terminals connected to the drain terminal of the transistor T1 and the second terminal of the two terminals connected to the plateline P/L.
The data input/output operation of the conventional FRAM is now described as follows. FIG. 3a is a timing diagram illustrating a write mode of the FRAM while FIG. 3b is a timing diagram illustrating a read-mode of the FRAM.
Referring to FIG. 3a, when a chip enable signal CSBpad applied externally transits from a high to low level and simultaneously a write enable signal WEBpad also transits from a high to low level, the array is enabled to start a write mode. Thereafter, when an address is decoded in a write mode, a pulse applied to a corresponding wordline transits from a “low” to “high” level, thereby selecting the cell.
In order to write a binary logic value “1” in the selected cell, a “high” signal is applied to a bitline while a “low” signal is applied to a plateline P/L. In order to write a binary logic value “0” in the cell, a “low” signal is applied to a bitline while a “high” signal is applied to a plateline P/L.
Referring to FIG. 3b, when a chip enable signal CSBpad externally transits from a “high” to “low” level, all bitlines are equalized to a “low” level by an equalization signal before selection of a required wordline.
After each bitline is deactivated, an address is decoded to transit a signal on the required wordline from a “low” to “high” level, thereby selecting a corresponding unit cell. A “high” signal is applied to a plateline of the selected cell to cancel a data Qs corresponding to the logic value “1” stored in the FRAM. If the logic value “0” is stored in the FRAM, a corresponding data Qns will not be destroyed.
The destroyed and non-destroyed data output different values, respectively, according to the above-described hysteresis loop characteristics. As a result, a sense amplifier senses logic values “1” or “0”. In other words, as shown in the hysteresis loop of FIG. 1, the state moves from ‘d’ to ‘f’ when the data is destroyed while the state moves from ‘a’ to ‘f’ when the data is not destroyed.
As a result, the destroyed data amplified by the enabled sense amplifier outputs a logic value “1” while the non-destroyed data amplified by the sense amplifier outputs a logic value “0”. After the sense amplifier amplifies the data, the data should be recovered into the original data. Accordingly, when a high signal is applied to the required wordline, the plateline is disabled from “high” to “low”.
The operation voltage of the FRAM ranges from low to high values. A boost voltage for driving a low voltage is used in a wordline WL, a plateline PL and a bitline BL in a FRAM cell operation. Here, it is helpful for reliability of chips not to generate excessive voltage in a boost circuit. Also, it is required not to apply the excessive voltage in a Burn-In test for testing reliability under a high temperature and a high voltage.
Because a conventional cell array is provided with a bitline connected to all cells in a column, the whole bitline should be driven to approach a cell. As a result, the driving load of the bitline increases, thereby slowing the driving speed.